Hereinafter, a conventional semiconductor device provided with a power supply variation detecting circuit will be described with reference to FIG. 11(refer to Patent Reference No. 1). As shown in FIG. 11, the semiconductor device is provided with two resister elements 103-106 between the power supply terminal 101 and the ground terminal 102. Further, it is provided with two-input comparators 107, 108. The comparator 107 receives an input from an one side input terminal that is obtained by dividing the power supply voltage 109 by the resister elements 105 and 106, and receives the reference voltage 112 from the other side input terminal. Further, there is provided a capacitance element 118 between a signal line connecting the one side terminal of the comparator 107 and the node 113 and the power supply terminal 116. Further, there is provided a logic AND circuit 119 operating output signals of the comparator 107, 108.
In the semiconductor device constituted as above, by comparing the divided power supply voltage 109 and the reference voltage 110 by the comparator 107, variations at positive side of the power supply voltage is detected, and by comparing the divided power supply voltage 111 and the reference voltage 112, variations at negative side of the power supply voltage is detected. When the power supply voltage varies toward the positive side, the voltage variations are capacitance-coupled by the capacitance element 117, and thereby the power supply voltage which is inputted to the one side input of the comparator 107 is varied, thereby becoming a reference voltage. The comparator 107 detects the voltage difference, and outputs a signal indicating t hat effect. Similarly, when the power supply voltage varies toward the negative side, the comparator 108 detects the voltage difference, and outputs a signal indicating that effect. The output signals of the comparators 107, and 108 are calculated by the logic AND circuit 119. By such a construction, the semiconductor device can output a logic signal indicating that the power supply voltage variation is detected.
Further, another conventional semiconductor device which is provided with a power supply voltage variation detection circuit will be described with reference to FIG. 12 (Patent Reference No. 2). In this semiconductor device, there are two inverter circuits 201, 202 which receive power supply voltage and ground voltage as inputs, and the output of the first stage inverter circuit 201 and the input of the second stage inverter circuit 202 are connected via the integration delay circuit comprising the resister element 203 and the capacitance element 204, and the output of the second stage inverter circuit 202 is connected to the input of the first stage inverter circuit 201. Thereby, when the voltage difference between the power supply voltage and the ground voltage varies steeply, the initial value which is previously stored is reversed, thereby outputting a logic signal indicating a steep increase or fall down of the voltage difference.    Patent reference No. 1: EP1160580A1    Patent reference No. 2: Japanese Published Patent Application Hei. 6-152358(page 7, FIG. 3)